TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-72. McASP0 Data Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
(Used when RSEL or XSEL
bits = 0 [these bits are located
in the RFMT or XFMT registers,
respectively].)
McASP0 receive buffers or McASP0 transmit buffers via
the Peripheral Data Bus.
01D0 1400 – 01D0 17FF
RBUF/XBUF
6.15.1.3 McASP0 Electrical Data/Timing
6.15.1.3.1 Multichannel Audio Serial Port (McASP) Timing
Table 6-73. Timing Requirements for McASP (see Figure 6-43 and Figure 6-44)(1)
-400
-500
-600
NO.
UNIT
MIN
MAX
1
2
3
4
tc(AHCKRX)
tw(AHCKRX)
tc(CKRX)
Cycle time, AHCLKR/X
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
10
25
10
10
3
ACLKR/X ext
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
tw(CKRX)
Pulse duration, ACLKR/X high or low
5
6
7
8
tsu(FRX-CKRX)
th(CKRX-FRX)
tsu(AXR-CKRX)
th(CKRX-AXR)
Setup time, AFSR/X input valid before ACLKR/X latches data
Hold time, AFSR/X input valid after ACLKR/X latches data
Setup time, AXR input valid before ACLKR/X latches data
Hold time, AXR input valid after ACLKR/X latches data
0
3
10
3
3
3
(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
264
Peripheral Information and Electrical Specifications
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