TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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7.23.2 Timers Electrical Data/Timing
The tables and figure below describe the timing requirements and switching characteristics of Timer0 through
Timer15 peripherals.
Table 7-84
(see Figure 7-59)
Timer Input Timing Requirements (1)
No.
Min
12C
12C
Max
Unit
ns
1
2
tw(TINPH)
tw(TINPL)
Pulse duration, high
Pulse duration, low
ns
End of Table 7-84
1
C = 1/SYSCLK1 frequency in ns.
Table 7-85
(see Figure 7-59)
Timer Output Switching Characteristics (1)
No.
Parameter
Pulse duration, high
Min
12C - 3
12C - 3
Max
Unit
ns
3
4
tw(TOUTH)
tw(TOUTL)
Pulse duration, low
ns
End of Table 7-85
1
C = 1/SYSCLK1 frequency in ns.
Figure 7-59
TIMIx
Timer Timing
1
2
4
3
TIMOx
7.24 Serial RapidIO (SRIO) Port
The SRIO port on the TMS320C6678 device is a high-performance, low pin-count interconnect aimed for
embedded markets. The use of the RapidIO interconnect in a baseband board design can create a homogeneous
interconnect environment, providing even more connectivity and control among the components. RapidIO is based
on the memory and device addressing concepts of processor buses where the transaction processing is managed
completely by hardware. This enables the RapidIO interconnect to lower the system cost by providing lower latency,
reduced overhead of packet data processing, and higher system bandwidth, all of which are key for wireless
interfaces. For more information, see the Serial RapidIO (SRIO) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 73.
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 227
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