TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 7-39
SPI Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
1
MASTER MODE
POLARITY = 0 PHASE = 0
2
3
SPICLK
5
4
6
MO(0)
7
MO(1)
MO(n−1)
MO(n)
MI(n)
SPIDOUT
SPIDIN
8
MI(0)
MI(1)
MI(n−1)
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPICLK
SPIDOUT
SPIDIN
6
5
5
5
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
4
MASTER MODE
POLARITY = 1 PHASE = 0
SPICLK
SPIDOUT
SPIDIN
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(n−1)
MASTER MODE
POLARITY = 1 PHASE = 1
SPICLK
SPIDOUT
SPIDIN
4
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
Figure 7-40
SPI Additional Timings for 4 Pin Master Mode with Chip Select Option
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPICLK
SPIDOUT
MO(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MI(0)
SPIDIN
SPISCSx
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Peripheral Information and Electrical Specifications 211
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