TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 7-70
SPI Switching Characteristics (Part 2 of 2)
(See Figure 7-39 and Figure 7-40)
No.
Parameter
Min
Max
Unit
6
6
6
6
toh(SPC-SDO)
toh(SPC-SDO)
toh(SPC-SDO)
toh(SPC-SDO)
Output hold time, SPIDOUT valid after receive edge of SPICLK except for final 0.5*tc - 2
bit. Polarity = 0 Phase = 0
ns
Output hold time, SPIDOUT valid after receive edge of SPICLK except for final 0.5*tc - 2
bit. Polarity = 0 Phase = 1
ns
ns
ns
Output hold time, SPIDOUT valid after receive edge of SPICLK except for final 0.5*tc - 2
bit. Polarity = 1 Phase = 0
Output hold time, SPIDOUT valid after receive edge of SPICLK except for final 0.5*tc - 2
bit. Polarity = 1 Phase = 1
Additional SPI Master Timings — 4 Pin Mode with Chip Select Option
19 td(SCS-SPC)
19 td(SCS-SPC)
19 td(SCS-SPC)
19 td(SCS-SPC)
20 td(SPC-SCS)
Delay from SPISCS[n] active to first SPICLK. Polarity = 0 Phase = 0
Delay from SPISCS[n] active to first SPICLK. Polarity = 0 Phase = 1
Delay from SPISCS[n] active to first SPICLK. Polarity = 1 Phase = 0
Delay from SPISCS[n] active to first SPICLK. Polarity = 1 Phase = 1
2*P2 - 5
2*P2 + 5
ns
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
2*P2 - 5 2*P2 + 5 ns
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
1*P2 - 5 1*P2 + 5 ns
Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 0
Phase = 0
20 td(SPC-SCS)
20 td(SPC-SCS)
20 td(SPC-SCS)
tw(SCSH)
Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 0
Phase = 1
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
1*P2 - 5 1*P2 + 5 ns
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
2*P2 - 5 ns
Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 1
Phase = 0
Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 1
Phase = 1
Minimum inactive time on SPISCS[n] pin between two transfers when
SPISCS[n] is not held using the CSHOLD feature.
End of Table 7-70
1 P2 = 1/SYSCLK7
210
Peripheral Information and Electrical Specifications
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