TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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7.13 SPI Peripheral
The serial peripheral interconnect (SPI) module provides an interface between the DSP and other SPI-compliant
devices. The primary intent of this interface is to allow for connection to a SPI ROM for boot. The SPI module on
C6678 is supported only in Master mode. Additional chip-level components can also be included, such as
temperature sensors or an I/O expander.
The C6678 SPI supports two modes, 3-pin and 4-pin. For the 4-pin chip-select mode, the C6678 supports up to two
chip selects.
7.13.1 SPI Electrical Data/Timing
7.13.1.1 SPI Timing
Table 7-69
See Figure 7-39)
SPI Timing Requirements
No.
Min
Max
Unit
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
7
7
7
7
8
8
8
8
tsu(SDI-SPC)
tsu(SDI-SPC)
tsu(SDI-SPC)
tsu(SDI-SPC)
th(SPC-SDI)
th(SPC-SDI)
th(SPC-SDI)
th(SPC-SDI)
Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0
Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1
Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0
Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1
Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0
Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1
Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0
Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1
2
2
2
2
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
End of Table 7-69
Table 7-70
SPI Switching Characteristics (Part 1 of 2)
(See Figure 7-39 and Figure 7-40)
No.
Parameter
Min
Max
Unit
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
1
2
3
4
tc(SPC)
Cycle Time, SPICLK, All Master Modes
3*P2 (1)
ns
tw(SPCH)
tw(SPCL)
td(SDO-SPC)
Pulse Width High, SPICLK, All Master Modes
Pulse Width Low, SPICLK, All Master Modes
0.5*tc - 1
0.5*tc - 1
ns
ns
ns
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.
Polarity = 0, Phase = 0.
5
5
5
5
2
2
2
2
4
4
4
5
5
5
5
td(SDO-SPC)
td(SDO-SPC)
td(SDO-SPC)
td(SPC-SDO)
td(SPC-SDO)
td(SPC-SDO)
td(SPC-SDO)
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.
Polarity = 0, Phase = 1.
ns
ns
ns
ns
ns
ns
ns
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK
Polarity = 1, Phase = 0
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK
Polarity = 1, Phase = 1
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on
SPICLK. Polarity = 0 Phase = 0
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK
Polarity = 0 Phase = 1
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK
Polarity = 1 Phase = 0
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK
Polarity = 1 Phase = 1
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 209
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