TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 7-42
CIC3 Event Inputs (Secondary Events for EDMA3CC0 and HyperLink) (Part 2 of 3)
Input Event # on CIC
System Interrupt
GPINT14
Description
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
GPIO interrupt
GPINT15
GPIO interrupt
TETBHFULLINT
System TETB is half full
TETBFULLINT
System TETB is full
TETBACQINT
System TETB acquisition has been completed
TETB0 is half full
TETBHFULLINT0
TETBFULLINT0
TETB0 is full
TETBACQINT0
TETB0 acquisition has been completed
TETB1 is half full
TETBHFULLINT1
TETBFULLINT1
TETB1 is full
TETBACQINT1
TETB1 acquisition has been completed
TETB2 is half full
TETBHFULLINT2
TETBFULLINT2
TETB2 is full
TETBACQINT2
TETB2 acquisition has been completed
TETB3 is half full
TETBHFULLINT3
TETBFULLINT3
TETB3 is full
TETBACQINT3
TETB3 acquisition has been completed
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for DDR3 EMIF1
Tracer sliding time window interrupt for MSMC SRAM bank0
Tracer sliding time window interrupt for MSMC SRAM bank1
Tracer sliding time window interrupt for MSMC SRAM bank2
Tracer sliding time window interrupt for MSMC SRAM bank3
Tracer sliding time window interrupt for CFG0 TeraNet
Tracer sliding time window interrupt for QM_SS CFG
Tracer sliding time window interrupt for QM_SS slave port
Tracer sliding time window interrupt for semaphore
HyperLink interrupt
TRACER_CORE_0_INTD
TRACER_CORE_1_INTD
TRACER_CORE_2_INTD
TRACER_CORE_3_INTD
TRACER_DDR_INTD
TRACER_MSMC_0_INTD
TRACER_MSMC_1_INTD
TRACER_MSMC_2_INTD
TRACER_MSMC_3_INTD
TRACER_CFG_INTD
TRACER_QM_CFG_INTD
TRACER_QM_DMA_INTD
TRACER_SM_INTD
VUSR_INT_O
TETBHFULLINT4
TETBFULLINT4
TETB4 is half full
TETB4 is full
TETBACQINT4
TETB4 acquisition has been completed
TETB5 is half full
TETBHFULLINT5
TETBFULLINT5
TETB5 is full
TETBACQINT5
TETB5 acquisition has been completed
TETB6 is half full
TETBHFULLINT6
TETBFULLINT6
TETB6 is full
TETBACQINT6
TETB6 acquisition has been completed
TETB7 is half full
TETBHFULLINT7
TETBFULLINT7
TETB7 is full
TETBACQINT7
TETB7 acquisition has been completed
Tracer sliding time window interrupt for individual core
TRACER_CORE_4_INTD
180
Peripheral Information and Electrical Specifications
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