TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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7.7.4 PASS PLL Input Clock Electrical Data/Timing
Table 7-32
PASS PLL Timing Requirements
(See Figure 7-28 and Figure 7-20)
No.
Min
Max
Unit
PASSCLK[P:N]
1
1
3
2
2
3
4
4
5
5
tc(PASSCLKN)
tc(PASSCLKP)
Cycle Time _ PASSCLKN cycle time
Cycle Time _ PASSCLKP cycle time
Pulse Width _ PASSCLKN high
Pulse Width _ PASSCLKN low
Pulse Width _ PASSCLKP high
Pulse Width _ PASSCLKP low
3.2
3.2
25
25
ns
ns
ns
ns
ns
ns
ps
ps
tw(PASSCLKN)
tw(PASSCLKN)
tw(PASSCLKP)
tw(PASSCLKP)
tr(PASSCLK_250mv)
tf(PASSCLK_250mv)
tj(PASSCLKN)
0.45*tc(PASSCLKN) 0.55*tc(PASSCLKN)
0.45*tc(PASSCLKN) 0.55*tc(PASSCLKN)
0.45*tc(PASSCLKP) 0.55*tc(PASSCLKP)
0.45*tc(PASSCLKP) 0.55*tc(PASSCLKP)
Transition time _ PASSCLK differential rise time (250 mV)
Transition time _ PASSCLK differential fall time (250 mV)
Jitter, peak_to_peak _ periodic PASSCLKN
50
50
350
350
0.02*tc(PASSCLKN) ps, pk-pk
0.02*tc(PASSCLKP) ps, pk-pk
tj(PASSCLKP)
Jitter, peak_to_peak _ periodic PASSCLKP
Figure 7-28
PASS PLL Timing
1
2
3
5
PASSCLKN
PASSCLKP
4
7.8 Enhanced Direct Memory Access (EDMA3) Controller
The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped
slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between
external memory and internal memory), performs sorting or subframe extraction of various data structures, services
event driven peripherals, and offloads data transfers from the device CPU.
There are 3 EDMA Channel Controllers on the C6678 DSP, EDMA3CC0, EDMA3CC1, and EDMA3CC2.
•
•
•
EDMA3CC0 has two transfer controllers: EDMA3TC1 and EDMA3TC2.
EDMA3CC1 has four transfer controllers: EDMA3TC0, EDMA3TC1, EDMA3TC2, and EDMA3TC3.
EDMA3CC2 has four transfer controllers: EDMA3TC0, EDMA3TC1, EDMA3TC2, and EDMA3TC3.
In the context of this document, EDMA3TCx associated with EDMA3CCy, and is referred to as EDMA3CCy TCx.
Each of the transfer controllers has a direct connection to the switch fabric. Section 4.2 ‘‘Switch Fabric Connections’’
lists the peripherals that can be accessed by the transfer controllers.
EDMA3CC0 is optimized to be used for transfers to/from/within the MSMC and DDR-3 Subsytems. The others are
to be used for the remaining traffic.
156
Peripheral Information and Electrical Specifications
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