ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
V
High-level output voltage (except PCI)
DV
= MIN, = MAX
I
OH
2.4
V
OH
DD
High-level output voltage (PCI)
[C6415T/C6416T only]
¶
I
= −0.5 mA,
DV
DD
= 3.3 V
0.9DV
DD
V
V
V
OHP
OL
OHP
Low-level output voltage (except PCI)
DV
= MIN,
I
= MAX
0.4
DD
OL
Low-level output voltage (PCI)
[C6415T/C6416T only]
¶
I
= 1.5 mA,
DV
= 3.3 V
DD
0.1DV
DD
OLP
OLP
V = V
SS
to DV
to DV
no opposing internal
opposing internal
opposing internal
I
DD
DD
DD
1
−50
200
uA
uA
uA
resistor
V = V
pullup resistor
I
SS
−200
50
−100
100
I
I
Input current (except PCI) [DC]
‡
V = V to DV
I
SS
‡
pulldown resistor
§
Input leakage current (PCI) [DC]
[C6415T/C6416T only]
I
I
0 < V < DV
IP DD
= 3.3 V
10
−8
−4
uA
mA
mA
IP
EMIF, CLKOUT4, CLKOUT6, EMUx
Timer, UTOPIA, TDO, GPIO (Excluding
GP[15:9, 2, 1]), McBSP
High-level output current [DC]
OH
¶
PCI/HPI
−0.5
mA
mA
EMIF, CLKOUT4, CLKOUT6, EMUx
8
Timer, UTOPIA, TDO, GPIO (Excluding
GP[15:9, 2, 1]), McBSP
4
¶
mA
I
Low-level output current [DC]
Off-state output current [DC]
OL
PCI/HPI
1.5
mA
uA
I
I
I
V = DV
O DD
or 0 V
20
OZ
#
Core supply current
Core supply current
CV
CV
CV
CV
DV
= 1.2 V, CPU clock = 720 MHz
= 1.2 V, CPU clock = 850 MHz
= 1.2 V, CPU clock = 1 GHz
= 1.1 V, CPU clock = 600 MHz
= 3.3 V, CPU clock = 720 MHz
713
824
952
558
151
mA
mA
mA
mA
mA
pF
CDD
CDD
DD
DD
DD
DD
DD
#
#
I
Core supply current
CDD
DDD
#
I
I/O supply current
C
C
Input capacitance
2
3
i
Output capacitance
pF
o
†
‡
§
¶
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.
These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Tables 4-3 and 4-4,
respectively.
#
Measured with average activity (50% high/50% low power). The actual current draw is highly application-dependent. For more details on core
and I/O activity, refer to the TMS320C6414T/15T/16T Power Consumption Application Report (literature number SPRAA45).
recommended clock and control signal transition behavior
All clocks and control signals must transition between V and V (or between V and V ) in a monotonic
IH
IL
IL
IH
manner.
77
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