TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
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SPRS230H–OCTOBER 2003–REVISED JUNE 2006
6.6 Clock Requirements and Characteristics
Table 6-8. Input Clock Frequency
PARAMETER
Resonator (X1/X2)
MIN
20
20
4
TYP MAX UNIT
35
Crystal (X1/X2)
35
MHz
100
fx
Input clock frequency
100-MHz device
60-MHz device
External oscillator/clock
source (XCLKIN or X1 pin)
4
60
fl
Limp mode SYSCLKOUT frequency range (with /2 enabled)
1-5
MHz
Table 6-9. XCLKIN(1) Timing Requirements - PLL Enabled
NO.
C8
MIN
MAX UNIT
tc(CI)
tf(CI)
Cycle time, XCLKIN
33.3
200
6
ns
ns
ns
%
C9
Fall time, XCLKIN
C10 tr(CI)
Rise time, XCLKIN
6
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45
45
55
55
%
(1) This applies to the X1 pin also.
Table 6-10. XCLKIN(1) Timing Requirements - PLL Disabled
NO.
MIN
10
MAX UNIT
C8
tc(CI)
Cycle time, XCLKIN
Fall time, XCLKIN
Rise time, XCLKIN
100-MHz device
60-MHz device
Up to 20 MHz
250
250
6
ns
16.67
C9
tf(CI)
ns
ns
ns
ns
%
20 MHz to 100 MHz
Up to 20 MHz
2
C10 tr(CI)
6
20 MHz to 100 MHz
2
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45
45
55
55
%
(1) This applies to the X1 pin also.
The possible configuration modes are shown in Table 3-16.
Table 6-11. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1)(2)
NO.
PARAMETER
Cycle time, XCLKOUT
MIN
10
TYP
MAX
UNIT
100-MHz device
60-MHz device
C1
tc(XCO)
ns
16.67
C3
C4
C5
C6
tf(XCO)
tr(XCO)
tw(XCOL)
tw(XCOH)
tp
Fall time, XCLKOUT
2
2
ns
ns
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
H-2
H-2
H+2
ns
H+2
ns
(3)
131072tc(OSCCLK)
cycles
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
98
Electrical Specifications
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