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TMS320F2809 参数 Datasheet PDF下载

TMS320F2809图片预览
型号: TMS320F2809
PDF下载: 下载PDF文件 查看货源
内容描述: - 12号的铝制车身绘( RAL 7032 ) []
分类和应用:
文件页数/大小: 134 页 / 1127 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F2809, TMS320F2808, TMS320F2806  
TMS320F2802, TMS320F2801, UCD9501  
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs  
www.ti.com  
SPRS230HOCTOBER 2003REVISED JUNE 2006  
Table 6-13. Reset (XRS) Timing Requirements  
MIN  
8tc(OSCCLK)  
8tc(OSCCLK)  
NOM  
MAX  
UNIT  
cycles  
cycles  
(1)  
tw(RSL1)  
Pulse duration, stable XCLKIN to XRS high  
Pulse duration, XRS low  
tw(RSL2)  
tw(WDRS)  
td(EX)  
Warm reset  
Pulse duration, reset pulse generated by  
watchdog  
512tc(OSCCLK)  
cycles  
Delay time, address/data valid after XRS high  
Oscillator start-up time  
32tc(OSCCLK)  
10  
cycles  
ms  
(2)  
tOSCST  
1
th(boot-mode)  
Hold time for boot-mode pins  
200tc(OSCCLK)  
cycles  
(1) In addition to the tw(RSL1) requirement, XRS has to be low at least for 1 ms after VDD reaches 1.5 V.  
(2) Dependent on crystal/resonator and board design.  
XCLKIN  
X1/X2  
OSCCLK/8  
XCLKOUT  
XRS  
User-Code Dependent  
OSCCLK * 5  
t
w(RSL2)  
User-Code Execution Phase  
t
d(EX)  
Address/Data/  
Control  
(Don’t Care)  
User-Code Execution  
(Internal)  
(A)  
t
Boot-ROM Execution Starts  
GPIO Pins as Input  
h(boot-mode)  
Boot-Mode  
Pins  
Peripheral/GPIO Function  
User-Code Dependent  
Peripheral/GPIO Function  
User-Code Execution Starts  
I/O Pins  
GPIO Pins as Input (State Depends on Internal PU/PD)  
User-Code Dependent  
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code  
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in  
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The  
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.  
Figure 6-6. Warm Reset  
Figure 6-7 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =  
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR  
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the  
PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating  
frequency, OSCCLK x 4.  
Electrical Specifications  
101