TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
www.ti.com
SPRS230H–OCTOBER 2003–REVISED JUNE 2006
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(Changed CPU Frequency)
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, t ) is
p
131072 OSCCLK Cycles Long.)
Figure 6-7. Example of Effect of Writing Into PLLCR Register
6.8 General-Purpose Input/Output (GPIO)
6.8.1 GPIO - Output Timing
Table 6-14. General-Purpose Output Switching Characteristics
PARAMETER
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
MIN
MAX
8
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
All GPIOs
All GPIOs
8
ns
25
MHz
GPIO
t
r(GPO)
t
f(GPO)
Figure 6-8. General-Purpose Output Timing
102
Electrical Specifications
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