TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
www.ti.com
SPRS230H–OCTOBER 2003–REVISED JUNE 2006
6.5.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
42 Ω
3.5 nH
Transmission Line
(Α)
Z0 = 50 Ω
(B)
Device Pin
4.0 pF
1.85 pF
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 6-3. 3.3-V Test Load Circuit
6.5.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 280x DSPs. Table 6-6 and Table 6-7 list the cycle times of various clocks.
Table 6-6. TMS320x280x Clock Table and Nomenclature (100-MHz Devices)
MIN
28.6
20
10
4
NOM
MAX UNIT
tc(OSC), Cycle time
Frequency
50
35
ns
MHz
ns
On-chip oscillator
clock
tc(CI), Cycle time
Frequency
250
100
500
100
2000
100
XCLKIN(1)
SYSCLKOUT
XCLKOUT
HSPCLK(2)
LSPCLK(2)
ADC clock
MHz
ns
tc(SCO), Cycle time
Frequency
10
2
MHz
ns
tc(XCO), Cycle time
Frequency
10
0.5
10
MHz
ns
tc(HCO), Cycle time
Frequency
20(3)
50(3)
40(3)
25(3)
100
100
MHz
ns
tc(LCO), Cycle time
Frequency
10
80
MHz
ns
tc(ADCCLK), Cycle time
Frequency
12.5
MHz
(1) This also applies to the X1 pin if a 1.8-V oscillator is used.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the default reset value if SYSCLKOUT = 100 MHz.
96
Electrical Specifications