TMDS261
www.ti.com ............................................................................................................................................................................................ SLLS953–DECEMBER 2008
SINK
VDD
(5V)
VCC
(3.3V)
HPD
5V
HPD
5V
HPDx
SDA SCL
mController
1kW
EQ
5V
47kW
SDAx
SCLx
S1
S2
SDA
SCL
CEC
SDA
SCL
CEC
CEC
LOGIC
SOURCE
in general HDMI output
E-EDID
CEC
Ax1/Bx1
Ax2/Bx2
Ax3/Bx3
Ax4/Bx4
CLK
D0
D1
D2
CLK
D0
D1
D2
HPD_SINK
1kW
CEC
PHY
3.3V
4.7kW
4.7kW
DDC_SDA
DDC_SCL
SDA_SINK
SCL_SINK
HDMI RX
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
VSadj
GND
4.02kW 10%
Figure 37. Two-Port HDMI Enabled DTV With TMDS261 – External Logic – CEC Commands Active
I2C INTERFACE NOTES
The I2C interface is used to access the internal registers of the TMDS261. I2C is a two-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA and
SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus
under control of the master device. The TMDS261 works as a slave and supports standard-mode transfer (100
kbps).
The basic I2C start and stop access cycles are shown in Figure 38.
The basic access cycle consists of the following:
•
•
•
•
A start condition
A slave address cycle
Any number of data cycles
A stop condition
SDA
SDA
SCL
SCL
S
P
Start
Condition
Stop
Condition
T0393-01
Figure 38. I2C Start and Stop Conditions
GENERAL I2C PROTOCOL
•
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
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