ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢉ ꢅꢃ
SLAS356 − DECEMBER 2001
PRINCIPLES OF OPERATION
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Table 10. I C Bus Conditions
CONDITION
STATUS
DESCRIPTION
A
Bus not busy
Both data and clock lines remain at high.
A high to low transition of the SDA line while the clock (SCL) is high determines a start condition.
All commands must proceed from a start condition.
B
Start data transfer
A low to high transition of the SDA line while the clock (SCL) is high determines a stop condition.
All operations must end with a stop condition.
C
D
Stop data transfer
Data valid
The state of the data line represents valid data when, after a start condition, the data line is stable
for the duration of the high period of the clock signal.
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I C bus protocols
The data on the line must be changed during the low period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
When addressed, the PCM codec generates an acknowledge after the reception of each byte. The master
device (microprocessor) must generate an extra clock pulse that is associated with this acknowledge bit.
The PCM codec must pull down the SDA line during the acknowledge clock pulse so that the SDA line is at stable
low state during the high period of the acknowledge related clock pulse. Setup and hold times must be taken
into account. During read operations, a master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave (PCM codec) must
leave the data line high to enable the master to generate the stop condition.
clock frequencies and sample rates
A fixed PCMSYN rate of 8 kHz determines the sampling rate.
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