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TLV320AIC1103PBSR 参数 Datasheet PDF下载

TLV320AIC1103PBSR图片预览
型号: TLV320AIC1103PBSR
PDF下载: 下载PDF文件 查看货源
内容描述: PCM编解码器 [PCM CODEC]
分类和应用: 解码器编解码器PC
文件页数/大小: 33 页 / 917 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢉꢉꢅ ꢃ  
SLAS356 − DECEMBER 2001  
PRINCIPLES OF OPERATION  
receive operation  
receive channel gain control  
The values in the receive PGA control registers control the gain in the receive path. PGA gain is set from 6 dB  
2
to 6 dB in 1-dB steps through the I C interface. The default receive channel gain is −1 dB.  
Table 5. Receive PGA Gain Control  
BIT NAME  
RP2  
RELATIVE GAIN  
RP3  
0
RP1  
0
RP0  
0
MIN  
5.8  
TYP  
6
MAX  
6.2  
UNIT  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
4.8  
5
5.2  
0
1
0
3.8  
4
4.2  
0
1
1
2.8  
3
3.2  
0
0
0
1.8  
2
2.2  
0
0
1
0.8  
1
1.2  
0
1
0
0.2  
−1.2  
2.2  
3.2  
4.2  
5.2  
6.2  
0
0.2  
0
1
1
−1  
−2  
−3  
−4  
−5  
−6  
0.8  
−1.8  
2.8  
3.8  
4.8  
5.8  
1
0
0
1
0
1
1
1
0
1
1
1
1
0
0
sidetone gain control  
The values in the sidetone PGA control registers control the sidetone gain. Sidetone gain is set from −12 dB  
2
to −24 dB in 2-dB steps through the I C interface. Sidetone can be muted by setting bit 7 of the power control  
register. The default sidetone gain is −12 dB.  
Table 6. Sidetone Gain Control  
BIT NAME  
RELATIVE GAIN  
ST2  
0
ST1  
0
ST0  
0
MIN  
TYP  
−12  
−14  
−16  
−18  
20  
22  
24  
MAX  
UNIT  
dB  
−12.2  
−14.2  
−16.2  
−18.2  
20.2  
22.2  
24.2  
11.8  
−13.8  
−15.8  
−17.8  
−19.8  
21.8  
23.8  
0
0
1
dB  
0
1
0
dB  
0
1
1
dB  
1
0
0
dB  
1
0
1
dB  
1
1
0
dB  
23  
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