TLK10002
SLLSE75 –MAY 2011
www.ti.com
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4.11:10 (HS_CDRFMULT[1:0]), 4.9:8 (HS_CDRTHR[1:0])
4.4:0 (HS_TWCRF[4:0]), 5.12:8 (HS_TWPOST1[4:0])
5.7:4 (HS_TWPRE[3:0]), 5.3:0 (HS_TWPOST2[3:0])
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LS Serial Configuration
Configure the following bits per the desired application:
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7.14:12 (LS_SWING[2:0]), 7.7:4 (LS_DE[3:0])
8.11:8 (LS_EQ [3:0]), 8.6:4 (LS_CDR [2:0])
Toggle HS_ENRX
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Write 1'b0 to 3.2 (HS_SERDES_CONTROL_2 = 0xA440)
Write 1'b1 to 3.2 (HS_SERDES_CONTROL_2 = 0xA444)
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Wait 10ms
Check SERDES PLL Status for Locked State
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Poll F.1 LS_PLL_LOCK (per channel) until it is asserted (high)
Poll F.0 HS_PLL_LOCK (per channel) until it is asserted (high)
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Issue Data path Reset
Write 1’b1 to E.3 DATAPATH_RESET
Clear Latched Registers
Read 0x0F CHANNEL_STATUS_1 to clear (per channel)
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Device provisioning has completed at this point
Periodically Check Device Operational Mode Status (Non-Errored Read Values Shown Below):
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Read 0x0F CHANNEL_STATUS_1 and verify the following bits:
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F.14 LA_SLAVE_STATUS (1’b1) (per channel)
F.13 HS_LOS (1’b0) (per channel)
F.12 HS_AZ_DONE (1’b1) (per channel)
F.11 HS_AGC_LOCKED (1’b1) (per channel)
F.10 HS_CHANNEL_SYNC (1’b1) (per channel)
F.8 HS_DECODE_INVALID (1’b0) (per channel)
F.7 TX_FIFO_UNDERFLOW (1’b0) (per channel)
F.6 TX_FIFO_OVERFLOW (1’b0) (per channel)
F.5 RX_FIFO_UNDERFLOW (1’b0) (per channel)
F.4 RX_FIFO_OVERFLOW (1’b0) (per channel)
F.3 RX_LS_OK (1’b1) (per channel).
F.2 TX_LS_OK (1’b1) (per channel).
F.1 LS_PLL_LOCK (1’b1) (per channel)
F.0 HS_PLL_LOCK (1’b1) (per channel)
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