TLC5970
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SBVS140 –MARCH 2010
Internal Latch Pulse Delay Time
Shifted in lower 36-bit data in the 40-bit shift register is latched into the latch selected by the higher four bits of
the shift register after the programmed time by the following code is passed from the last rising edge of SCLK.
The next SCLK rising edge for new data inputs must be input after over two clocks of the internal oscillator clock
period from the shift register is latched.
Table 15. Internal Latch Pulse Delay Time Selection Truth Table
INTERNAL LATCH PULSE DELAY TIME (µs)
FB DATA
(Binary)
FB DATA
(Decimal)
FB DATA
(Hex)
MINIMUM
0.3
MAXIMUM
0.8
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0.6
1.3
2
1.3
2.3
3
2.6
4.3
4
5.3
8.3
5
10
16
6
21
33
7
42
65
8
85
129
9
170
341
682
1365
2730
5461
10922
257
10
11
12
13
14
15
513
1025
2049
4097
8193
16385
EEPROM2 Write Data Latch (Register Address = 1101b)
The EEPROM2 write data latch data bit assignments are shown in Table 16 and Figure 33.
Table 16. EEPROM2 Write Data Latch Bit Assignment
BIT NUMBER
6-0
BIT NAME
DCOUT0
DCOUT1
DCOUT2
DESCRIPTION
Dot correction data for OUT0 (data = 00h to 7Fh, factory default = 7Fh)
Dot correction data for OUT1 (data = 00h to 7Fh, factory default = 7Fh)
Dot correction data for OUT2 (data = 00h to 7Fh, factory default = 7Fh)
13-7
20-14
No EEPROM bits (7-bit data). Data cannot be stored in these bits even if
data are written to these bits.
27-21
35-28
—
Write command. When data are written to the EEPROM1 write data latch,
these data must be 5Ah (01011010b).
WRCMD2
EEPROM2 Write Data Latch
MSB
35
LSB
0
28
27
No
21
No
20
14
13
7
6
Write
Command
Bit 7
Write
OUT2
OUT2
OUT1
OUT1
OUT0
OUT0
DC Data
Bit 0
¼
¼
¼
¼
¼
Command EEPROM
Bit 6
EEPROM DC Data
Bit 0 Bit 6
DC Data DC Data
Bit 0
Bit 6
DC Data DC Data
Bit 0
Bit 6
Bit 0
Figure 33. EEPROM2 Write Data Latch Bit Assignment
Copyright © 2010, Texas Instruments Incorporated
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