TLC5928
www.ti.com ................................................................................................................................................. SBVS120A–JULY 2008–REVISED SEPTEMBER 2008
STATUS INFORMATION DATA (SID)
The latched LED open detection (LOD) error and pre-thermal warning (PTW) in the SID data latch are shifted out
onto the SOUT pin with each rising edge of SCLK. If a PTW is reported, all LOD error bits are set to '1'. The SID
data are written over the data in the on/off control shift register at the rising edge of LAT. Therefore, the previous
data in the on/off control shift register are lost when SID information is latched in. Figure 20 shows the SID bit
assignments. See Figure 7 for the read timing of SID.
When the IC is powered on, the initial LOD data are invalid. Therefore, LOD data must be read after the rising
edge of BLANK. Table 3 shows a truth table for LOD and PTW.
Table 3. LOD and PTW Truth Table
CONDITION
SID DATA
LED is connected (VOUTn > VLOD
)
'0' (low level at SOUT)
LED open detection (LODn)
Pre-termal warning (PTW)
LED is opened or shorted to GND
(VOUTn ≤ VLOD and output on)
'1' (high level at SOUT); set to the bit that has an
LED error condition
IC temperature is low (IC temperature ≤ T(PTW)
)
Depend LED open error
IC temperature is high (IC temperature > T(PTW)
)
All bits = '1' (high level at SOUT)
SID Data Latch (1 Bit ´ 16 Channels)
MSB
LSB
15
14
13
12
11
4
3
2
1
0
OUT15
LOD Data
(LOD 15)
OUT15
LOD Data
(LOD 14)
OUT15
LOD Data
(LOD 13)
OUT15
LOD Data
(LOD 12)
OUT15
LOD Data
(LOD 3)
OUT15
LOD Data
(LOD 2)
OUT15
LOD Data
(LOD 1)
OUT15
LOD Data
(LOD 0)
¼
All Bits Become ‘1’ When the IC is in a PTW (Pre-Thermal Warning) Condition
¼
MSB
15
LSB
0
14
13
12
11
4
3
2
1
SIN
On/Off Data On/Off Data On/Off Data On/Off Data
for
OUT14
On/Off Data On/Off Data
for
OUT2
On/Off Data On/Off Data
for
OUT0
¼
for
OUT15
for
OUT13
for
OUT12
for
OUT3
for
OUT1
SOUT
SCLK
The 16 bits in the SID latch are loaded into the on/off shift register at the rising edge of LAT.
SID Control Shift Register (1 Bit ´ 16 Channels)
Figure 20. Status Information Data Configuration
Copyright © 2008, Texas Instruments Incorporated
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