TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000
PRINCIPLES OF OPERATION
line control register (LCR)
This register controls the data communication format. The word length, number of stop bits, and parity type are
selected by writing the appropriate bits to the LCR. Table 10 shows line control register bit settings.
Table 10. Line Control Register (LCR) Bit Settings
BIT NO.
BIT SETTINGS
1:0
Specifies the word length to be transmitted or received.
00 – 5 bits
01 – 6 bits
10 – 7 bits
11 – 8 bits
2
Specifies the number of stop bits:
0 – 1 stop bits (word length = 5, 6, 7, 8)
1 – 1.5 stop bits (word length = 5)
1 – 2 stop bits (word length = 6, 7, 8)
3
4
5
0 = No parity
1 = A parity bit is generated during transmission and the receiver checks for received parity.
0 = Odd parity is generated (if LCR(3) = 1)
1 = Even parity is generated (if LCR(3) = 1)
Selects the forced parity format (if LCR(3) = 1)
If LCR(5) = 1 and LCR(4) = 0 = the parity bit is forced to 1 in the transmitted and received data.
If LCR(5) = 1 and LCR(4) = 1 = the parity bit is forced to 0 in the transmitted and received data.
6
7
Break control bit.
0 = Normal operating condition
1 = Forces the transmitter output to go low to alert the communication terminal.
0 = Normal operating condition
1 = Divisor latch enable
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
