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TL16C752BPTG4 参数 Datasheet PDF下载

TL16C752BPTG4图片预览
型号: TL16C752BPTG4
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 V双64字节FIFO的UART [3.3-V DUAL UART WITH 64-BYTE FIFO]
分类和应用: 先进先出芯片
文件页数/大小: 36 页 / 503 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TL16C752B  
3.3-V DUAL UART WITH 64-BYTE FIFO  
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000  
PRINCIPLES OF OPERATION  
receiver holding register (RHR)  
The receiver section consists of the receiver holding register (RHR) and the receiver shift register (RSR). The  
RHRisactuallya64-byteFIFO. TheRSRreceivesserialdatafromRXterminal. Thedataisconvertedtoparallel  
data and moved to the RHR. The receiver section is controlled by the line control register. If the FIFO isdisabled,  
locationzerooftheFIFOisusedtostorethecharacters. (Note:Inthiscasecharactersareoverwrittenifoverflow  
occurs.) If overflow occurs, characters are lost. The RHR also stores the error status bits associated with each  
character.  
transmit holding register (THR)  
The transmitter section consists of the transmit holding register (THR) and the transmit shift register (TSR). The  
transmit holding register is actually a 64-byte FIFO. The THR receives data and shifts it into the TSR where it  
is converted to serial data and moved out on the TX terminal. If the FIFO is disabled, the FIFO is still used to  
store the byte. Characters are lost if overflow occurs.  
FIFO control register (FCR)  
This is a write-only register which is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and  
receiver trigger levels, and selecting the type of DMA signalling. Table 9 shows FIFO control register bit settings.  
Table 9. FIFO Control Register (FCR) Bit Settings  
BIT NO.  
BIT SETTINGS  
0
0 = Disable the transmit and receive FIFOs  
1 = Enable the transmit and receive FIFOs  
1
2
0 = No change  
1 = Clears the receive FIFO and resets counter logic to zero. Will return to zero after clearing FIFO.  
0 = No change  
1 = Clears the transmit FIFO and resets counter logic to zero. Will return to zero after clearing FIFO.  
3
0 = DMA Mode 0  
1 = DMA MOde 1  
5:4  
Sets the trigger level for the TX FIFO:  
00 – 8 spaces  
01 – 16 spaces  
10 – 32 spaces  
11 – 56 spaces  
7:6  
Sets the trigger level for the RX FIFO:  
00 – 8 characters  
01 – 16 characters  
10 – 56 characters  
11 – 60 characters  
NOTE: FCR[54] can only be modified and enabled when EFR[4] is set. This is because the transmit trigger level is regarded as an enhanced  
function.  
25  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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