TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000
PRINCIPLES OF OPERATION
Table 8 lists and describes the TL16C752 internal registers.
Table 8. TL16C752A Internal Registers
READ/
WRITE
Addr REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
000
000
001
RHR
THR
IER
bit 7
bit 7
bit 6
bit 6
bit 5
bit 5
bit 4
bit 4
bit 3
bit 3
bit 2
bit 2
bit 1
bit 1
bit 0
bit 0
Read
Write
0/CTS
0/RTS
0/Xoff
sleep
0/X Sleep
Modem
status
interrupt
Rx line
status
interrupt
THR
empty
interrupt
Rx data Read/Write
available
interrupt
†
mode
interrupt
interrupt
†
†
†
mode
enable
enable
010
010
011
100
101
FCR
IIR
Rx trigger
level
Rx trigger
level
0/TX
0/TX
DMA
mode
select
Resets
Resets
Enables
FIFOs
Write
Read
trigger
trigger
Tx FIFO
Rx FIFO
†
level
†
level
†
FCR(0)
FCR(0)
0/CTS,
0/Xoff
Interrupt
priority
Bit 2
Interrupt
priority
Bit 1
Interrupt
priority
Bit 0
Interrupt
status
†
RTS
LCR
MCR
LSR
DLAB and
EFR
enable
Break
control bit
Sets parity Parity type
select
Parity
enable
No. of stop
bits
Word
length
Word
length
Read/Write
Read/Write
Read
1x or 1x/4
clock
TCR and
TLR
enable
0/Xon Any
0/Enable
loopback
IRQ
enable
OP
FIFO Rdy
enable
RTS
DTR
0/Error in
Rx FIFO
THR and
TSR empty
THR
empty
Break
interrupt
Framing
error
Parity
error
Overrun
error
Data in
receiver
110
111
000
001
010
MSR
SPR
DLL
CD
bit 7
RI
bit 6
DSR
bit 5
CTS
bit 4
∆CD
bit 3
∆RI
bit 2
bit 2
bit 10
∆DSR
bit 1
∆CTS
bit 0
bit 0
bit 8
Read
Read/Write
Read/Write
Read/Write
bit 7
bit 6
bit 5
bit 4
bit 3
bit 1
DLH
EFR
bit 15
bit 14
Auto-RTS
bit 13
bit 12
bit 11
bit 9
Auto-CTS
Special
character
detect
Enable
S/W flow
control
Bit 3
S/W flow
control
Bit 2
S/W flow
control
Bit 1
S/W flow Read/Write
control
Bit 0
enhanced
†
functions
100
101
110
111
110
111
111
Xon1
Xon2
bit 7
bit 7
bit 7
bit 7
bit 7
bit 7
0
bit 6
bit 6
bit 6
bit 6
bit 6
bit 6
0
bit 5
bit 5
bit 5
bit 5
bit 5
bit 5
bit 4
bit 3
bit 3
bit 3
bit 3
bit 3
bit 3
0
bit 2
bit 2
bit 2
bit 2
bit 2
bit 2
0
bit 1
bit 1
bit 1
bit 1
bit 1
bit 1
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
bit 4
Xoff1
bit 4
Xoff2
bit 4
TCR
bit 4
TLR
bit 4
FIFO Rdy
RX FIFO
B status
RX FIFO
A status
TX FIFO
B status
TX FIFO
A status
†
The shaded bits in the above table can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.
NOTE: Refer to the notes under Table 7 for more register access information.
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