TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000
Start
Bit
Stop
Bit
Data Bits (5–8)
D3 D4
D0
D1
D2
D5
D6
D7
TX (A–B)
Parity
Bit
Next
Data
Start
Bit
5 Data Bits
6 Data Bits
7 Data Bits
t
d12
Active
Tx Ready
INT (A–B)
IOW
t
t
d14
d13
Active
Active
16 Baud Rate Clock
Figure 18. Transmit Timing
Start
Bit
Stop
Bit
Data Bits (5–8)
D0
D1
D2
D3
D4
D5
D6
D7
TX (A–B)
Next
Parity
Bit
Data
Start
Bit
Active
IOW
D0–D7
Byte 1
t
d18
t
d17
Active
Transmitter Ready
TXRDY (A–B)
Transmitter
Not Ready
Figure 19. Transmit Ready Timing in Non-FIFO Mode
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