TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000
timing requirements T = –40°C to 85°C, V
= 3.3 V ± 10% (unless otherwise noted)
CC
A
(see Figures 12–19)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IOR delay from chip select
Read cycle delay
0
‡
d1
2t
ns
d2
p(I)
Delay from IOR to data
28.5
15
ns
d3
Data disable time
ns
d4
IOW delay from chip select
Write cycle delay
10
‡
ns
d5
2t
ns
d6
p(I)
Delay from IOW to output
100 pF load
100 pF load
100 pF load
50
70
70
ns
d7
Delay to set interrupt from MODEM input
Delay to reset interrupt from IOR
Delay from stop to set interrupt
Delay from IOR to reset interrupt
Delay from stop to interrupt
Delay from initial INT reset to transmit start
Delay from IOW to reset interrupt
Delay from stop to set RXRDY
Delay from IOR to reset RXRDY
Delay from IOW to set TXRDY
Delay from start to reset TXRDY
ns
d8
ns
†
d9
1
d10
d11
d12
d13
d14
d15
d16
d17
d18
d19
h1
Rclk
70
100 pF load
ns
100
24
70
1
ns
†
8
ns
Clock
µs
1
70
16
ns
†
‡
4P
†
Delay between successive assertion of IOW and IOR
Chip select hold time from IOR
Chip select hold time from IOW
Data hold time
0
0
ns
ns
h2
15
0
ns
h3
Address hold time
ns
h4
Hold time from XTAL1 clock ↓ to IOW or IOR release
Clock cycle period
20
20
ns
h5
, t
p1 p2
ns
Oscillator/clock speed
V
CC
= 3 V
48
MHz
ns
p3
Reset pulse width
200
0
(RESET)
su1
Address setup time
ns
Data setup time
16
ns
su2
Setup time from IOW or IOR assertion to XTAL1 clock ↑
IOR strobe width
20
‡
ns
su3
2t
2t
ns
w1
p(I)
§
‡
IOW strobe width
ns
w2
p(I)
†
‡
Baud rate
t
= input clock period
p(I)
17
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