TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
parallel port timing requirements over recommended ranges of supply voltage and operating
free-air temperature (see Note 16 and Figures 15, 16, and 17)
MIN
tsu7
th6
tw6
td10
td11
tw7
tw8
td12
td13
td14
td15
td16
Setup time, data valid before STB
↓
Hold time, data valid after STB
↑
Pulse duration, STB
↓
Delay time, BUSY
↑
to ACK
↓
Delay time, BUSY
↓
to ACK
↓
Pulse duration, BUSY
↑
Pulse duration, ACK
↓
Delay time, BUSY
↑
after STB
↑
Delay time, INT2
↓
after ACK
↓
(see Note 17)
Delay time, INT2
↑
after ACK
↑
(see Note 17)
Delay time, INT2
↑
after ACK
↑
(see Note 17)
Delay time, INT2
↓
after IOR
↑
(see Note 17)
1
1
1
Defined by printer
Defined by printer
Defined by printer
Defined by printer
Defined by printer
22
20
24
25
ns
ns
ns
ns
MAX
UNIT
µs
µs
µs
NOTES: 16. These parameters are not production tested.
17. td13 – td16 are all measured with a 15-pF load.
PARAMETER MEASUREMENT INFORMATION
tw1
CLK (XTAL1)
0.8 V
tw2
fclock = 16 MHz MAX
2V
2V
0.8 V
Figure 1. CLK Voltage Waveform
2.54 V
Device Under Test
680
Ω
TL16C552A
82 pF
(see Note A)
NOTE A: This includes scope and jig capacitance.
Figure 2. Output Load Circuit
10
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