TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
Byte #16
IOW
(WR THR)
50%
Start of
Byte #16
Start
Data
Parity
Stop
SOUT
t
t
d8
pd5
FIFO Full
TXRDY
50%
50%
Figure 8. Transmitter Ready Mode 1 Timing Waveforms
RCLK
t
8 CLK Cycles
pd6
CLK
TL16C450 Mode
SIN
(receiver input
data)
Start
Data Bits 5–8
Parity
Stop
Sample
CLK
t
d9
Interrupt
(data ready or
RCVR ERR)
50%
50%
t
pd7
Active
IOR
50%
Figure 9. Receiver Timing Waveforms
13
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