TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
line status register (LSR) (continued)
NOTE:
The LSR may be written to. However, this function is intended only for factory test. It should be
considered as read only by applications software.
Table 9. Line Status Register Bits
LSR BITS
1
Ready
Error
0
LSR0 data ready (DR)
Not ready
No error
LSR1 overrun error (OE)
LSR2 parity error (PE)
Error
No error
LSR3 framing error (FE)
Error
No error
LSR4 break interrupt (BI)
Break
No break
Not empty
Not empty
No error in FIFO
LSR5 transmitter holding register empty (THRE)
LSR6 transmitter empty (TEMT)
LSR7 receiver FIFO error
Empty
Empty
Error in FIFO
master reset
After power up, the ACE RESET input should be held low for one microsecond to reset the ACE circuits to an
idle mode until initialization. A low on RESET causes the following:
It initializes the transmitter and receiver clock counters.
It clears the LSR except for transmitter shift register empty (TEMT) and transmit holding register empty
(THRE), which are set. The MCR is also cleared. All of the discrete lines, memory elements, and
miscellaneous logic associated with these register bits are also cleared or turned off. The LCR, divisor
latches, receiver buffer register, and transmitter holding buffer register are not affected.
Following the removal of the reset condition (RESET high), the ACE remains in idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bit in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE. A summary of the effect of a reset on the ACE is given in Table 10.
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