TAS5711
SLOS600 –DECEMBER 2009
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Output Mode and MUX Selection
2.0 BTL AD
Reg setting
0x20 (23) = 0
0x20 (19) = 0
0x05 (3) = X
0x05 (2) = 0
PWM1
PWM2
PWM3
PWM4
A
B
C
D
CH1_audio
CH2_audio
2.0 BTL BD
Reg setting
0x20 (23) = 1
0x20 (19) = 1
0x05 (3) = X
0x05 (2) = 0
PWM1
PWM2
PWM3
PWM4
A
B
C
D
CH1_audio
CH2_audio
2.1 SE, BTL-AD
Reg setting
0x20 (23) = 0
0x20 (19) = 0
0x05 (3) = 0
0x05 (2) = 1
PWM1
PWM2
PWM3
PWM4
A
B
C
D
CH1_audio
CH2_audio
CH3_audio
2.1 SE, BTL-BD
Reg setting
0x20 (23) = 0
0x20 (19) = 0
0x05 (3) = 1
0x05 (2) = 1
PWM1
PWM2
PWM3
PWM4
A
B
C
D
CH1_audio
CH2_audio
CH3_audio
B0378-01
Figure 51. Output Mode and MUX Selection
2.1-Mode Support
The TAS5711 uses a special mid-Z ramp sequence to reduce click and pop in SE-mode and 2.1-mode
operation.To enable the mid-Z ramp, register 0x05 bit D7 must be set to 1. To enable 2.1 mode, register 0x05 bit
D2 must be set to 1. The SSTIMER pin should be left floating in this mode.
Single-Filter PBTL-Mode Support
The TAS5711 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected before
the LC filter. In order to put the part in PBTL configuration, drive PBTL (pin 8) HIGH. This synchronizes the
turnoff of half-bridges A and B (and similarly C/D) if an overcurrent condition is detected in either half-bridge.
There is a pulldown resistor on the PBTL pin that configures the part in BTL mode if the pin is left floating.
PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should
be written with a value of 0x01 10 32 45. Also, the PWM shutdown register (0x19) should be written with a value
of 0x3A.
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