TAS5707
www.ti.com ........................................................................................................................................................................................... SLOS556–NOVEMBER 2008
PIN FUNCTIONS (continued)
PIN
NAME
TYPE
5-V
TOLERANT
TERMINATION
DESCRIPTION
(1)
(2)
NO.
8
NC
–
AO
AO
O
No connection
OC_ADJ
OSC_RES
OUT_A
OUT_B
OUT_C
OUT_D
PDN
7
Analog overcurrent programming. Requires resistor to ground.
Oscillator trim resistor. Connect an 18.2-kΩ 1% resistor to DVSSO.
Output, half-bridge A
16
1
46
39
36
19
O
Output, half-bridge B
O
Output, half-bridge C
O
Output, half-bridge D
DI
5-V
Pullup
Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the Noise Shaper and initiating PWM stop
sequence.
PGND_AB
PGND_CD
PLL_FLTM
PLL_FLTP
PVDD_A
PVDD_B
PVDD_C
PVDD_D
RESET
47, 48
37, 38
10
P
P
Power ground for half-bridges A and B
Power ground for half-bridges C and D
PLL negative loop filter terminal
AO
AO
P
11
PLL positive loop filter terminal
2, 3
Power supply input for half-bridge output A
Power supply input for half-bridge output B
Power supply input for half-bridge output C
Power supply input for half-bridge output D
44, 45
40, 41
34, 35
25
P
P
P
DI
5-V
Pullup
Reset, active-low. A system reset is generated by applying a logic low
to this pin. RESET is an asynchronous control signal that restores the
DAP to its default conditions, and places the PWM in the hard mute
state (tristated).
SCL
24
21
DI
DI
5-V
5-V
I2C serial control clock input
SCLK
Pulldown
Pulldown
Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
I2C serial control data interface input/output
SDA
23
22
DIO
DI
5-V
5-V
SDIN
Serial audio data input. SDIN supports three discrete (stereo) data
formats.
SSTIMER
6
AI
Controls ramp time of OUT_X to minimize pop. Leave this pin floating
for BD mode. Requires capacitor of 2.2 nF to GND in AD mode. The
capacitor determines the ramp time.
STEST
FAULT
26
14
DI
Factory test pin. Connect directly to DVSS.
DO
Backend error indicator. Asserted LOW for over temperature, over
current, over voltage, and under voltage error conditions. De-asserted
upon recovery from error condition.
VR_ANA
VR_DIG
VREG
12
18
31
P
P
P
Internally regulated 1.8-V analog supply voltage. This pin must not be
used to power external devices.
Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
Digital regulator output. Not to be used for powering external circuitry.
Copyright © 2008, Texas Instruments Incorporated
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