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SLOS556 – NOVEMBER 2008
SERIAL AUDIO PORTS SLAVE MODE
over recommended operating conditions (unless otherwise noted)
PARAMETER
f
SCLKIN
t
su1
t
h1
t
su2
t
h2
Frequency, SCLK 32 × f
S
, 48 × f
S
, 64 × f
S
Setup time, LRCLK to SCLK rising edge
Hold time, LRCLK from SCLK rising edge
Setup time, SDIN to SCLK rising edge
Hold time, SDIN from SCLK rising edge
LRCLK frequency
SCLK duty cycle
LRCLK duty cycle
SCLK rising edges between LRCLK rising edges
t
(edge)
tr /
tf
(SCLK/LRCLK)
LRCLK clock edge with respect to the falling edge of SCLK
Rise/fall time for SCLK/LRCLK
t
r
SCLK
(Input)
t
(edge)
t
h1
t
su1
LRCLK
(Input)
t
h2
t
su2
SDIN
T0026-04
TEST
CONDITIONS
C
L
= 30 pF
MIN
1.024
10
10
10
10
8
40%
40%
32
–1/4
TYP
MAX
12.288
UNIT
MHz
ns
ns
ns
ns
48
50%
50%
48
60%
60%
64
1/4
8
t
f
kHz
SCLK
edges
SCLK
period
ns
Figure 2. Slave Mode Serial Data Interface Timing
Copyright © 2008, Texas Instruments Incorporated
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