TAS5707
SLOS556–NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
48-TERMINAL, HTQFP PACKAGE (TOP VIEW)
PHP Package
(Top View)
48 47 46 45 44 43 42 41 40 39 38 37
OUT_A
PVDD_A
PVDD_A
BST_A
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD_OUT
VREG
1
36
35
34
33
32
31
30
29
28
27
26
25
2
3
4
GVDD_OUT
SSTIMER
OC_ADJ
NC
5
6
TAS5707
7
AGND
8
GND
AVSS
9
DVSS
PLL_FLTM
10
11
12
DVDD
PLL_FLTP
VR_ANA
STEST
RESET
13 14 15 16 17 18 19 20 21 22 23 24
P0075-01
PIN FUNCTIONS
PIN
NAME
AGND
TYPE
5-V
TOLERANT
TERMINATION
DESCRIPTION
(1)
(2)
NO.
30
13
9
P
P
P
P
P
P
P
P
P
P
P
P
DI
DI
Analog ground for power stage
3.3-V analog power supply
Analog 3.3-V supply ground
AVDD
AVSS
BST_A
BST_B
BST_C
BST_D
DVDD
DVSSO
DVSS
GND
4
High-side bootstrap supply for half-bridge A
High-side bootstrap supply for half-bridge B
High-side bootstrap supply for half-bridge C
High-side bootstrap supply for half-bridge D
3.3-V digital power supply
43
42
33
27
17
28
29
5, 32
20
15
Oscillator ground
Digital ground
Analog ground for power stage
Gate drive internal regulator output
Input serial audio data left/right clock (sample rate clock)
Master clock input
GVDD_OUT
LRCLK
5-V
5-V
Pulldown
Pulldown
MCLK
(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic
levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input).
6
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5707
TI [ TEXAS INSTRUMENTS ]
