SLOS556 – NOVEMBER 2008...........................................................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED APPLICATION DIAGRAM
3.3 V
8 V–24 V
AVDD/DVDD
PVDD
OUT_A
LRCLK
Digital
Audio
Source
SCLK
MCLK
SDIN
BST_B
BST_A
LC
Left
OUT_B
2
I C
Control
SDA
SCL
OUT_C
BST_C
LC
Control
Inputs
RESET
PDN
OUT_D
BST_D
Right
PLL_FLTP
Loop
Filter*
PLL_FLTM
B0264-03
*Refer to user's guide for Loop Filter details.
2
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