TAS5715
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SLOS645 –AUGUST 2010
Table 3. Serial Control Interface Register Summary (continued)
NO. OF
BYTES
INITIALIZATION
VALUE
SUBADDRESS
REGISTER NAME
CONTENTS
0x34
ch2_bq[4]
ch2_bq[5]
ch2_bq[6]
20
u[31:26], b0[25:0]
u[31:26], b1[25:0]
u[31:26], b2[25:0]
u[31:26], a1[25:0]
u[31:26], a2[25:0]
u[31:26], b0[25:0]
u[31:26], b1[25:0]
u[31:26], b2[25:0]
u[31:26], a1[25:0]
u[31:26], a2[25:0]
u[31:26], b0[25:0]
u[31:26], b1[25:0]
u[31:26], b2[25:0]
u[31:26], a1[25:0]
u[31:26], a2[25:0]
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 A14C
0x0000 5395
0x0000 0000
0x0080 0000
0x0008 0000
0x0078 0000
0x35
0x36
20
20
0x37
0x38
0x39
0x3A
0x3B
EQ CRC
4
4
u[31:16], EQ CRC [15:0]
u[31:16], DRC CRC [15:0]
Reserved(2)
DRC CRC
8
8
Reserved(2)
DRC1 softening filter alpha
u[31:26], ae[25:0]
u[31:26], oe[25:0]
DRC1 softening filter
omega
0x3C
DRC1 attack rate
DRC1 release rate
8
0x0000 0100
0xFFFF FF00
0x0080 0000
0x0008 0000
0xFFF8 0000
0x3D
0x3E
8
8
Reserved(2)
DRC2 softening filter alpha
u[31:26], ae[25:0]
u[31:26], oe[25:0]
DRC2 softening filter
omega
0x3F
0x40
DRC2 attack rate
8
8
u[31:26], at[25:0]
u[31:26], rt[25:0]
T1[31:0] (9.23 format)
T1'[31:0]
0x0008 0000
0xFFF8 0000
0x0800 0000
0x07FF FFFF
0x0000 0000
0x0074 0000
0x0073 FFFF
0x0000 0000
0x0002 0020
DRC2 release rate
DRC1 attack threshold
DRC1 release threshold
0x42
0x43
4
8
Reserved(2)
DRC2 attack threshold
DRC2 release threshold
T2[31:0] (9.23 format)
T2'[31:0]
Reserved(2)
0x45
0x46
4
4
DRC and DC DETECT
control
Description shown in subsequent section
0x47–0x4F
0x50
4
4
8
Reserved(2)
Bank switch control
Ch 1 output mixer
Description shown in subsequent section
Ch 1 output mix1[1]
0x0F70 8000
0x0080 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x51
Ch 1 output mix1[0]
0x52
0x53
Ch 2 output mixer
Ch 1 input mixers
8
Ch 2 output mix2[1]
Ch 2 output mix2[0]
Channel-1 input mixers can be accessed using I2C
subaddresses 0x70–0x73 using 4-byte access
16
(2) Reserved registers should not be accessed.
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