TAS5727
SLOS670 –NOVEMBER 2010
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2-Channel I2S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
24 Clks
24 Clks
LRCLK
Right Channel
Left Channel
SCLK
SCLK
MSB
LSB
1
MSB
LSB
24-Bit Mode
23 22
17 16
13 12
9
5
1
8
4
0
5
1
4
0
3
2
0
23 22
19 18
15 14
17 16
13 12
9
5
1
8
4
0
5
1
4
0
3
2
1
20-Bit Mode
19 18
16-Bit Mode
15 14
9
8
9
8
T0092-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 17. I2S 48-fS Format
2-Channel I2S (Philips Format) Stereo Input
16 Clks
16 Clks
LRCLK
Right Channel
Left Channel
SCLK
SCLK
MSB
LSB
1
MSB
LSB
16-Bit Mode
15 14 13 12 11 10
9
8
5
4
3
2
0
15 14 13 12 11 10
9
8
5
4
3
2
1
T0266-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 18. I2S 32-fS Format
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
20
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