TAS5705
SLOS549–JUNE 2008...................................................................................................................................................................................................... www.ti.com
MODULATION LIMIT REGISTER (0x10)
Set modulation limit. See the appropriate power stage data sheet for recommended modulation limits.
Table 17. Modulation Limit Register (0x10)
LIMIT
[DCLKs]
D7
D6
D5
D4
D3
D2
D1
D0
MIN WIDTH [DCLKs]
MODULATION LIMIT
–
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
0
0
0
0
0
1
1
1
1
–
0
0
1
1
0
0
1
1
–
0
1
0
1
0
1
0
1
–
1
2
3
4
5
6
7
8
2
4
99.2%
98.4%
6
97.7%
8
96.9%
10
12
14
16
96.1%
95.3%
94.5%
93.8%
RESERVED
INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, 0x14, 0x15, 0x16)
Internal PWM channels 1, 2, 3, 4, 5, and 6 are mapped into registers 0x11, 0x12 ,0x13, 0x14, 0x15, and 0x16.
Table 18. Channel Interchannel Delay Register Format
BITS DEFINITION
D7
0
D6
0
D5
D4
D3
D2
D1
D0
FUNCTION
Minimum absolute delay, 0 DCLK cycles, default for
0
0
0
0
0
0
(1)
channel 0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
Maximum positive delay, 31 × 4 DCLK cycles
Maximum negative delay, –32 × 4 DCLK cycles
Unused bits
A
SUBADDRESS
0x11
D7
0
D6
1
D5
0
D4
0
D3
1
D2
1
D1
0
D0 Delay = (value) × 4 DCLK cycles
(1)
0
0
0
0
0
0
Default value for channel 1
Default value for channel 2
Default value for channel 3
Default value for channel 4
Default value for channel 5
Default value for channel 6
-18 ( 0XB8)
24 ( 0X60)
-24 ( 0XA0)
18 ( 0X48)
-3 ( 0XF4)
3 ( 0X0C)
(1)
(1)
(1)
(1)
(1)
0x12
0
0
1
1
0
1
0
0x13
0
0
0
1
1
1
0
0x14
0
1
1
0
0
1
0
0x15
1
1
0
1
0
0
0
0x16
1
0
0
1
0
0
0
(1) Default values are in bold.
OFFSET REGISTER (0x17)
The offset register is mapped into 0x17.
Table 19. Channel Offset Register Format
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
(1)
Minimum absolute offset, 0 DCLK cycles, default for channel 0
1
1
1
1
1
1
1
1
Maximum absolute offset, 255 DCLK cycles
(1) Default values are in bold.
54
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