1G79
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
Logic Diagram
2
C
CLK
C
C
4
TG
Q
C
C
C
C
1
D
TG
TG
TG
C
C
C
FUNCTION TABLE
INPUTS
OUTPUT
Q
CLK
D
H
L
H
L
↑
↑
L
X
Q
0
ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC AUC
AUP
3.3V
AUP AUP
2.5V 1.8V
AUP
1.1V
PARAMETER
MAX or MIN
UNIT
2.5V
1.8V
ICC
IOH
IOL
MAX
MAX
MAX
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
0.01
-9
9
0.01 0.0009 0.0009 0.0009 0.0009 mA
-8
8
-4
4
-3.1
3.1
-1.9
1.9
-1.1
1.1
mA
mA
TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS
AUP
3.3V
AUP
2.5V
AUP
1.8V
AUP
1.1V
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC AUC
PARAMETER
INPUT
OUTPUT
MAX or MIN
2.5V
1.8V
MIN
MIN
160
2.5
1.2
1.2
0.5
4.5
4.5
160
2.5
1.3
1.3
1.0
5
160
2.5
1.4
1.4
0.4
7
160
2.5
2.2
2.6
0.3
9.9
9.9
260
1.9
0.6
1
0
4.5
4.5
250
1.7
0.7
1
0
5.7
5.7
240
1.6
0.9
1.1
0
160
2.2
1.4
1.8
0
fmax
tw
275
1.7
0.7
0.7
0.1
1.8
1.8
250
1.7
0.5
0.5
0
CLK high or low
Before CLK ↑, Data high
Before CLK ↑, Data low
Data after CLK ↑
tsu
MIN
th
tPLH
tPHL
MIN
2.4
2.4
8
8
14.4
14.4
CLK
Q
MAX
5
7
UNIT fmax : MHz other : ns
104
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