1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
Logic Diagram
6
CLR
1
C
CLK
C
C
3
5
Q
Q
TG
C
C
C
C
2
7
D
TG
TG
TG
C
C
C
PRE
FUNCTION TABLE
INPUTS
PRE CLR CLK
OUTPUTS
D
Q
Q
L
X
H
H
H
H
L
H
H
H
X
X
↑
↑
L
X
X
H
L
H
L
H
L
L
H
L
H
X
Q
Q
0
0
ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
AUC
2.5V
AUC AUP
1.8V 3.3V
AUP
2.5V
AUP AUP
1.8V 1.1V
PARAMETER
MAX or MIN
UNIT
MAX
MAX
MAX
0.01
-9
0.01 0.0009 0.0009 0.0009 0.0009
mA
mA
mA
I
I
I
CC
-8
8
-4
4
-3.1
3.1
-1.9
1.9
-1.1
1.1
OH
OL
9
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT
AUC
2.5V
AUC
1.8V
AUP
3.3V
AUP
2.5V
AUP
1.8V
AUP
1.1V
MAX or MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
160
2
130
2
60
2
50
2
f
275
1
250
1
max
CLK
Pulse duration
t
w
low
2
2
2
2
1
1
PRE or CLR
high
0.5
1
0.5
1
1
1.3
1.2
0.5
0
0.4
0.4
0.4
0.3
1.8
1.8
1.8
1.8
2.1
2.1
0.5
0.5
0.7
0.3
2.4
2.4
2.4
2.4
2.8
2.8
Data
low
1
Setup time, before CLK ↑
t
su
inactive
0.5
0
0.5
0
0.5
0
PRE or CLR
t
t
t
t
t
t
t
Hold time, data after CLK ↑
h
5.3
5.3
5.2
5.2
5.8
5.8
7
10.4
10.4
9.9
9.9
10.8
10.8
21.8
21.8
20.3
20.3
21.4
21.4
PLH
PHL
PLH
PHL
PLH
PHL
CLK
Q
MAX
MAX
MAX
7
6.7
6.7
7.4
7.4
CLK
Q
PRE or CLR
Q or Q
UNIT fmax : MHz other : ns
103
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.