ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢃꢅ
ꢇꢈ ꢉꢈ ꢊꢋꢌ ꢀꢈ ꢉ ꢍꢋꢌ ꢎꢏ ꢐ ꢆꢑ ꢀ ꢀꢐ ꢏ
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory read/write timing (continued)
The following table defines memory write timing parameters for IOSTRB.
timing parameters for a memory (IOSTRB = 0) write (see Figure 13)
320C30-40
320C30-50
†
NO.
UNIT
MIN
0*
0*
0*
0*
9
MAX
MIN
0*
0*
0*
0*
8
MAX
27
28
29
30
33
34
t
t
t
t
t
t
Delay time, H1 high to IOSTRB low
Delay time, H1 high to IOSTRB high
Delay time, H1 low to (X)R/W high
Delay time, H1 low to (X)A valid
Setup time, (X)RDY before H1 high
Hold time, (X)RDY after H1 high
9
9
9
9
8
8
8
8
ns
ns
ns
ns
ns
ns
d(H1H-IOSL)
d(H1H-IOSH)
d[H1L-(X)RWH]
d[H1L-(X)A]
su[(X)RDY-H1H]
h[H1H-(X)RDY]
0
0
35
36
37
t
t
t
Delay time, H1 low to XR/W low
Valid time, (X)D after H1 high
Hold time, (X)D after H1 low
0*
13
25
0*
11
20
ns
ns
ns
d(H1L-XRWL)
v[H1H(X)D]W
h[H1L-(X)D]W
0
0
†
Numbers in this column match those used in Figure 13.
* This parameter is not production tested.
H3
H1
27
28
IOSTRB
(X)R/W
29
35
30
(X)A
(X)D
37
36
33
34
(X)RDY
Figure 13. Timing for Memory (IOSTRB = 0) Write
21
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