ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢃꢅ
ꢇꢈ ꢉꢈ ꢊꢋꢌ ꢀꢈ ꢉ ꢍꢋꢌ ꢎꢏ ꢐ ꢆꢑ ꢀ ꢀꢐ ꢏ
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory read/write timing
The following table defines memory read/write timing parameters for (M)STRB.
timing parameters for a memory [(M)STRB = 0] read/write (see Figure 10 and Figure 11)
320C30-40
320C30-50
†
NO.
UNIT
MIN MAX
MIN MAX
11
12
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, H1 low to (M)STRB low
Delay time, H1 low to (M)STRB high
Delay time, H1 high to R/W low
0*
0*
0*
0*
0*
0*
14
16
0*
8
10
6
0*
0*
0*
0*
0*
0*
10
14
0*
6
4
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d[H1L-(M)SL]
d[H1L-(M)SH]
d(H1H-RWL)
d[H1H-(X)RWL]
d(H1L-A)
13.1
13.2
14.1
14.2
15.1
15.2
16
9
7
Delay time, H1 high to (X)R/W low
Delay time, H1 low to A valid
13
11
9
11
9
Delay time, H1 low to (X)A valid
8
d[H1L-(X)A]
Setup time, D valid before H1 low (read)
Setup time, (X)D before H1 low (read)
Hold time, (X)D after H1 low (read)
su(D-H1L)R
su[(X)DR-H1L]R
h[H1L-(X)D]R
su(RDY-H1H)
su[(X)RDY-H1H]
h[H1H-(X)RDY]
d[H1H-(X)RWH]W
v[H1L(X)D]W
h[H1H-(X)D]W
d(H1H-A)
17.1
17.2
18
Setup time, RDY before H1 high
Setup time, (X)RDY before H1 high
Hold time, (X)RDY after H1 high
9
8
0
0
19
Delay time, H1 high to (X)R/W high (write)
Valid time, (X)D after H1 low (write)
Hold time, (X)D after H1 high (write)
Delay time, H1 high to A valid on back-to-back write cycles (write)
Delay time, H1 high to (X)A valid on back-to-back write cycles (write)
Delay time, (X)RDY from A valid
9
7
20
17
14
21
0*
0*
22.1
22.2
26
15
21
7*
12
18
6*
d[H1H-(X)A]
d[A-(X)RDY]
†
Numbers in this column match those used in Figure 10 and Figure 11.
* This parameter is not production tested.
17
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