ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢅ
ꢇ ꢈꢉ ꢈꢊꢋ ꢌ ꢀꢈ ꢉꢍ ꢋ ꢌ ꢎ ꢏꢐ ꢆꢑ ꢀꢀ ꢐꢏ
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory read/write timing (continued)
The following table defines memory read timing parameters for IOSTRB.
timing parameters for a memory (IOSTRB = 0) read (see Figure 12)
320C30-40
320C30-50
†
NO.
UNIT
MIN MAX
MIN MAX
27
28
29
30
31
32
33
34
t
t
t
t
t
t
t
t
Delay time, H1 high to IOSTRB low
Delay time, H1 high to IOSTRB high
Delay time, H1 low to (X)R/W high
Delay time, H1 low to (X)A valid
Setup time, (X)D before H1 high
Hold time, (X)D after H1 high
0*
0*
0*
0*
13
0*
9
9
9
9
9
0*
0*
0*
0*
11
0*
8
8
8
8
8
ns
ns
ns
ns
ns
ns
ns
ns
d(H1H-IOSL)
d(H1H-IOSH)
d[H1L-(X)RWH]
d[H1L-(X)A]
su[(X)D-H1H]R
h[H1H-(X)D]R
su[(X)RDY-H1H]
h[H1H-(X)RDY]
Setup time, (X)RDY before H1 high
Hold time, (X)RDY after H1 high
0
0
†
Numbers in this column match those used in Figure 12.
* This parameter is not production tested.
H3
H1
28
27
IOSTRB
(X)R/W
29
30
(X)A
(X)D
31
32
33
34
(X)RDY
Figure 12. Timing for Memory (IOSTRB = 0) Read
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443