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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
X2/CLKIN, H1, and H3 timing
The following table defines the timing parameters for the X2/CLKIN, H1, and H3 interface signals. See the
RESET timing in Figure 20 for CLKIN to H1 and H3 delay specification.
timing parameters for X2/CLKIN, H1, H3 (see Note 5, Figure 7, Figure 8, and Figure 9)
320C30-40
320C30-50
†
NO.
UNIT
MIN
MAX
MIN
MAX
1
2
3
4
5
6
7
8
9
t
t
t
t
t
t
t
t
t
t
t
Fall time, CLKIN
5*
5*
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f(CI)
Pulse duration, CLKIN low, t
= MIN (see Note 9)
9
9
7
7
w(CIL)
w(CIH)
r(CI)
c(CI)
Pulse duration, CLKIN high, t
Rise time, CLKIN
= MIN (see Note 9)
c(CI)
5*
303
3
5*
303
3
Cycle time, CLKIN
25
20
c(CI)
Fall time, H1/H3
f(H)
Pulse duration, H1/H3 low (see Note 10)
Pulse duration, H1/H3 high (see Note 10)
Rise time, H1/H3
P − 5
P − 6
P − 5
P − 6
w(HL)
w(HH)
r(H)
3
4
3
4
9.1
10
Delay time, from H1 low to H3 high or from H3 low to H1 high
Cycle time, H1/H3
0
0
d(HL-HH)
c(H)
50
606
40
606
†
Numbers in this column match those used in Figure 7, Figure 8, and Figure 9.
* This parameter is not production tested.
NOTES: 5. All input and output voltage levels are TTL compatible.
9. Rise and fall times, assuming a 35 − 65% duty cycle, are incorporated within this specification (see Figure 6).
10. P = t
c(CI)
5
4
1
3
X2/CLKIN
(1.5 V)
2
Figure 7. X2/CLKIN Timing
15
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