SPNS174
–
SEPTEMBER 2011
4.7
Clock Monitoring
The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low
power oscillator (LPO).
The LPO provides two different clock sources
–
a low frequency (CLK80K) and a high frequency
(CLK10M).
The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN
frequency falls out of a frequency window, the CLKDET flags this condition in the global status register
(GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the CLK10M clock (limp
mode clock).
The valid OSCIN frequency range is defined as: f
CLK10M
/ 4
<
f
OSCIN
<
f
CLK10M
* 4.
4.7.1
Clock Monitor Timings
Table 4-15. LPO and Clock Detection
Parameter
MIN
oscillator fail frequency - lower threshold, using
untrimmed LPO output
oscillator fail frequency - higher threshold, using
untrimmed LPO output
1.375
22
5.5
Type
2.4
38.4
9.6
MAX
4.875
78
19.5
10
900
150
36
85
180
100
2000
27
20
Unit
MHz
MHz
MHz
µs
µs
µA
kHz
µs
µs
µA
µA
Clock Detection
LPO - HF oscillator
untrimmed frequency
startup time from STANDBY (LPO BIAS_EN High for
at least 900ms)
cold startup time
ICC, CLK10M and CLK80K active
LPO - LF oscillator
untrimmed frequency
startup time from STANDBY (LPO BIAS_EN High for
at least 900ms)
cold startup time
ICC, only CLK80K active
LPO
total ICC STANDBY current
guaranteed fail
lower
threshold
guaranteed pass
upper
guaranteed fail
threshold
1.375
4.875
22
78
f[MHz]
Figure 4-8. LPO and Clock Detection, Untrimmed CLK10M
4.7.2
External Clock (ECLK) Output Functionality
The ECLK pin can be configured to output a pre-scaled clock signal indicative of an internal device clock.
This output can be externally monitored as a safety diagnostic.
4.7.3
Dual Clock Comparators
The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by
counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of
spec, an error signal is generated. For example, the DCC1 can be configured to use CLK10M as the
reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration
allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.
Copyright
©
2011, Texas Instruments Incorporated
System Information and Electrical Specifications
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