SPNS174
–
SEPTEMBER 2011
4.6.3
Clock Test Mode
The RM4x platform architecture defines a special mode that allows various clock signals to be brought out
on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is very
useful for debugging purposes and can be configured via the CLKTEST register in the system module.
Table 4-14. Clock Test Mode Options
SEL_ECP_PIN
=
CLKTEST[3-0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SIGNAL ON ECLK
Oscillator
Main PLL free-running clock output
Reserved
EXTCLKIN1
CLK80K
CLK10M
Secondary PLL free-running clock output
EXTCLKIN2
GCLK
RTI Base
Reserved
VCLKA1
Reserved
VCLKA3
VCLKA4
Reserved
SEL_GIO_PIN
=
CLKTEST[11-8]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SIGNAL ON N2HET1[12]
Oscillator Valid Status
Main PLL Valid status
Reserved
Reserved
Reserved
CLK10M Valid status
Secondary PLL Valid Status
Reserved
CLK80K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PRODUCT PREVIEW
66
System Information and Electrical Specifications
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