SPNS174
–
SEPTEMBER 2011
An additional use of this module is to measure the frequency of a selectable clock source, using the input
clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a
fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width
pulse (1 cycle) after a pre-programmed number of pulses. This pulse sets as an error signal if counter 1
does not reach 0 within the counting window generated by counter 0.
4.7.3.1
•
•
•
•
Features
Takes two different clock sources as input to two independent counter blocks.
One of the clock sources is the known-good, or reference clock; the second clock source is the "clock
under test."
Each counter block is programmable with initial, or seed values.
The counter blocks start counting down from their seed values at the same time; a mismatch from the
expected frequency for the clock under test generates an error signal which is used to interrupt the
CPU.
Mapping of DCC Clock Source Inputs
Table 4-16. DCC1 Counter 0 Clock Sources
CLOCK SOURCE [3:0]
CLOCK NAME
oscillator (OSCIN)
high frequency LPO
test clock (TCK)
4.7.3.2
PRODUCT PREVIEW
68
others
0x5
0xA
Table 4-17. DCC1 Counter 1 Clock Sources
KEY [3:0]
others
CLOCK SOURCE [3:0]
-
0x0
0x1
0x2
0xA
0x3
0x4
0x5
0x6
0x7
0x8 - 0xF
CLOCK NAME
N2HET1[31]
Main PLL free-running clock output
reserved
low frequency LPO
high frequency LPO
flash HD pump oscillator
EXTCLKIN1
EXTCLKIN2
ring oscillator
VCLK
Table 4-18. DCC2 Counter 0 Clock Sources
CLOCK SOURCE [3:0]
others
0xA
CLOCK NAME
oscillator (OSCIN)
test clock (TCK)
Table 4-19. DCC2 Counter 1 Clock Sources
KEY [3:0]
others
0xA
CLOCK SOURCE [3:0]
-
00x0 - 0x7
0x8 - 0xF
CLOCK NAME
N2HET2[0]
Reserved
VCLK
System Information and Electrical Specifications
focus.ti.com:
Copyright
©
2011, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
