SPNS174
–
SEPTEMBER 2011
4.6.1.4
External Clock Inputs
The device supports up to two external clock inputs. This clock input must be a square wave input. The
electrical and timing requirements for these clock inputs are specified below.
Table 4-12. External Clock Timing and Electrical Specifications
Parameter
f
EXTCLKx
t
w(EXTCLKIN)H
t
w(EXTCLKIN)L
v
iL(EXTCLKIN)
v
iH(EXTCLKIN)
Description
External clock input frequency
EXTCLK high-pulse duration
EXTCLK low-pulse duration
Low-level input voltage
High-level input voltage
6
6
-0.3
2
0.8
VCCIO + 0.3
Min
Max
80
Unit
MHz
ns
ns
V
V
4.6.2
4.6.2.1
Clock Domains
Clock Domain Descriptions
The table below lists the device clock domains and their default clock sources. The table also shows the
system module control register that is used to select an available clock source for each clock domain.
Clock Domain Name
HCLK
GCLK
Default Clock
Source
OSCIN
OSCIN
Clock Source
Selection Register
GHVSRC
GHVSRC
•
•
•
•
•
•
Description
Is disabled via the CDDISx registers bit 1
Used for all system modules including DMA, ESM
Always the same frequency as HCLK
In phase with HCLK
Is disabled separately from HCLK via the CDDISx registers bit 0
Can be divided by 1up to 8 when running CPU self-test (LBIST)
using the CLKDIV field of the STCCLKDIV register at address
0xFFFFE108
Always the same frequency as GCLK
2 cycles delayed from GCLK
Is disabled along with GCLK
Gets divided by the same divider setting as that for GCLK when
running CPU self-test (LBIST)
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Is disabled separately from HCLK via the CDDISx registers bit 2
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Frequency must be an integer multiple of VCLK frequency
Is disabled separately from HCLK via the CDDISx registers bit 3
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Is disabled separately from HCLK via the CDDISx registers bit 8
Defaults to VCLK as the source
Is disabled via the CDDISx registers bit 4
Defaults to VCLK as the source
Is disabled via the CDDISx registers bit 5
Defaults to VCLK as the source
Frequency can be as fast as HCLK frequency.
Is disabled via the CDDISx registers bit 10
GCLK2
OSCIN
GHVSRC
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
VCLK
OSCIN
GHVSRC
VCLK2
OSCIN
GHVSRC
VCLK3
OSCIN
GHVSRC
VCLKA1
VCLKA2
VCLKA3_S
VCLK
VCLK
VCLK
VCLKASRC
VCLKASRC
VCLKACON
Copyright
©
2011, Texas Instruments Incorporated
System Information and Electrical Specifications
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PRODUCT PREVIEW
Table 4-13. Clock Domain Descriptions
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