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RM46L450PGET 参数 Datasheet PDF下载

RM46L450PGET图片预览
型号: RM46L450PGET
PDF下载: 下载PDF文件 查看货源
内容描述: RM46Lx50 16位/ 32位RISC闪存微控制器 [RM46Lx50 16/32-Bit RISC Flash Microcontroller]
分类和应用: 闪存微控制器
文件页数/大小: 172 页 / 2534 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号RM46L450PGET的Datasheet PDF文件第5页浏览型号RM46L450PGET的Datasheet PDF文件第6页浏览型号RM46L450PGET的Datasheet PDF文件第7页浏览型号RM46L450PGET的Datasheet PDF文件第8页浏览型号RM46L450PGET的Datasheet PDF文件第10页浏览型号RM46L450PGET的Datasheet PDF文件第11页浏览型号RM46L450PGET的Datasheet PDF文件第12页浏览型号RM46L450PGET的Datasheet PDF文件第13页  
RM46L450  
RM46L850  
www.ti.com  
SPNS184 SEPTEMBER 2012  
2.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
AD1IN[15] AD1IN[22]  
AD1IN[11]  
/
AD2IN[11]  
N2HET1 MIBSPI5 MIBSPI1 MIBSPI1 MIBSPI5 MIBSPI5 N2HET1  
CLK  
AD1IN  
[06]  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VSS  
VSS  
TMS  
NC  
CAN3RX AD1EVT  
/
AD2IN[15] AD2IN[06]  
/
VSSAD  
VSSAD 19  
[10]  
NCS[0]  
SIMO  
NENA  
SIMO[0]  
[28]  
AD1IN[08] AD1IN[14] AD1IN[13]  
N2HET1 MIBSPI1 MIBSPI1 MIBSPI5 MIBSPI5 N2HET1  
NENA  
AD1IN  
[04]  
AD1IN  
[02]  
VSS  
TDI  
TCK  
nRST  
NC  
TDO  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
nTRST  
NC  
CAN3TX  
NC  
/
AD2IN[08] AD2IN[14] AD2IN[13]  
/
/
VSSAD 18  
AD1IN[09]  
[08]  
CLK  
SOMI  
SOMI[0]  
[0]  
AD1IN[10]  
/
AD2IN[10]  
EMIF_  
nWE  
MIBSPI5  
SOMI[1]  
MIBSPI5 MIBSPI5 N2HET1  
[31]  
EMIF_  
nCS[3]  
EMIF_  
nCS[2]  
EMIF_  
nCS[4]  
EMIF_  
nCS[0]  
AD1IN  
[05]  
AD1IN  
[03]  
AD1IN  
[01]  
NC  
NC  
NC  
/
AD2IN[09]  
17  
SIMO[3] SIMO[2]  
AD1IN[23] AD1IN[12] AD1IN[19]  
/
AD2IN[07] AD2IN[12] AD2IN[03]  
EMIF_  
BA[1]  
MIBSPI5  
SIMO[1]  
MIBSPI5 MIBSPI5  
SOMI[3] SOMI[2]  
RTCK  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
/
/
ADREFLO VSSAD 16  
ADREFHI VCCAD 15  
AD1IN[21] AD1IN[20]  
EMIF_  
DATA[0]  
EMIF_  
DATA[1]  
EMIF_  
DATA[2]  
EMIF_  
DATA[3]  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
/
/
AD2IN[05] AD2IN[04]  
AD1IN[18]  
/
AD2IN[02]  
N2HET1  
[26]  
AD1IN  
[07]  
AD1IN  
[0]  
nERROR  
NC  
VCCIO  
VCCIO  
VCCIO  
VCCIO  
VCC  
VCCIO  
VCCIO  
VCC  
VCC  
VCCIO  
VCCIO  
VCCIO  
VCCIO  
VCCIO  
VCCIO  
VCCPLL  
VCC  
NC  
NC  
14  
13  
12  
11  
AD1IN[17] AD1IN[16]  
/
AD2IN[01] AD2IN[0]  
N2HET1 N2HET1  
[19]  
EMIF_BA[0]  
EMIF_nOE  
/
NC  
NC  
NC  
[17]  
N2HET1  
[04]  
MIBSPI5  
NCS[3]  
ECLK  
VSS  
VSS  
VCC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VCC  
VSS  
VSS  
VSS  
VCC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VCC  
VSS  
VSS  
NC  
NC  
NC  
NC  
N2HET1 N2HET1  
[14] [30]  
EMIF_  
nDQM[1]  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
EMIF_  
ADDR[12]  
MIBSPI3  
NCS[0]  
EMIF_  
nDQM[0]  
10 CAN1TX CAN1RX  
NC  
GIOB[3] 10  
N2HET1  
[27]  
EMIF_  
ADDR[11]  
EXTCLKI  
N2  
MIBSPI3 MIBSPI3  
CLK  
EMIF_  
ADDR[5]  
9
8
7
6
5
4
3
2
1
NC  
NC  
VCC  
VCCIO  
VCCIO  
VCCIO  
VCCIO  
NC  
9
8
7
6
5
4
3
2
1
NENA  
EMIF_  
ADDR[10]  
MIBSPI3 MIBSPI3  
SIMO  
EMIF_  
ADDR[4]  
EMIF_  
DATA[15]  
NC  
VCCP  
VCCIO  
VCCIO  
NC  
SOMI  
EMIF_  
ADDR[9]  
N2HET1  
[09]  
EMIF_  
ADDR[3]  
EMIF_  
DATA[14]  
nPORRST  
LINRX  
LINTX  
NC  
MIBSPI5  
NCS[1]  
EMIF_  
ADDR[8]  
N2HET1 MIBSPI5  
[05] NCS[2]  
EMIF_  
ADDR[2]  
EMIF_  
DATA[13]  
GIOA[4]  
NC  
VCCIO  
VCCIO  
FLTP2  
VCCIO  
FLTP1  
VCC  
VCC  
VCCIO  
VCCIO  
NC  
EMIF_ EMIF_  
ADDR[7] ADDR[1]  
MIBSPI3 N2HET1  
[02]  
EMIF_  
DATA[4]  
EMIF_  
DATA[5]  
EMIF_  
DATA[6]  
EMIF_  
DATA[7]  
EMIF_  
DATA[8]  
EMIF_  
DATA[9]  
EMIF_  
DATA[10]  
EMIF_  
DATA[11]  
EMIF_  
DATA[12]  
GIOA[0] GIOA[5]  
N2HET1 N2HET1  
NC  
NCS[1]  
EMIF_ EMIF_  
ADDR[6] ADDR[0]  
N2HET1 N2HET1  
[21]  
EMIF_  
nCAS  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
[16]  
[12]  
[23]  
N2HET1 N2HET1 MIBSPI3  
NCS[3]  
SPI2  
NENA  
N2HET1 MIBSPI1 MIBSPI1  
[11] NCS[1] NCS[2]  
MIBSPI1  
NCS[3]  
EMIF_  
CLK  
EMIF_  
CKE  
N2HET1  
[25]  
SPI2  
NCS[0]  
EMIF_  
nWAIT  
EMIF_  
nRAS  
N2HET1  
[06]  
GIOA[6]  
NC  
NC  
[29]  
[22]  
MIBSPI3  
NCS[2]  
SPI2  
SOMI  
KELVIN_  
GND  
N2HET1 N2HET1 MIBSPI1  
[20]  
N2HET1  
[01]  
VSS  
GIOA[1]  
SPI2 CLK GIOB[2] GIOB[5] CAN2TX GIOB[6] GIOB[1]  
GIOB[0]  
TEST  
VSS  
[13]  
NCS[0]  
SPI2  
SIMO  
N2HET1  
[18]  
N2HET1 N2HET1  
[24]  
N2HET1 N2HET1  
[07]  
VSS  
A
VSS  
B
GIOA[2]  
C
GIOA[3] GIOB[7] GIOB[4] CAN2RX  
OSCIN  
K
OSCOUT GIOA[7]  
NC  
R
VSS  
V
VSS  
W
[15]  
[03]  
D
E
F
G
H
J
L
M
N
P
T
U
Figure 2-2. ZWT Package Pinout. Top View  
Note: Balls can have multiplexed functions. Only the default function is depicted in above diagram.  
Copyright © 2012, Texas Instruments Incorporated  
Device Package and Terminal Functions  
9
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