RM46L450
RM46L850
SPNS184 –SEPTEMBER 2012
www.ti.com
5.12.2 Ethernet RMII Timing
5
4
6
7
9
8
10
Figure 5-24. RMII Timing Diagram
Table 5-38. RMII Timing Requirements
NO.
Parameter
Value
Unit
MIN
NOM
MAX
1
2
3
6
tc(REFCLK)
Cycle time, RMII_REF_CLK
-
20
-
-
ns
ns
ns
ns
tw(REFCLKH)
tw(REFCLKL)
tsu(RXD-REFCLK)
Pulse width, RMII_REF_CLK High
Pulse width, RMII_REF_CLK Low
7
7
4
13
13
-
-
Input setup time, RMII_RXD valid before
RMII_REF_CLK High
-
7
8
th(REFCLK-RXD)
Input hold time, RMII_RXD valid after
RMII_REF_CLK High
2
4
2
4
2
2
2
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
tsu(CRSDV-REFCLK)
th(REFCLK-CRSDV)
tsu(RXER-REFCLK)
th(REFCLK-RXER)
td(REFCLK-TXD)
Input setup time, RMII_CRSDV valid before
RMII_REF_CLK High
9
Input hold time, RMII_CRSDV valid after
RMII_REF_CLK High
-
10
11
4
Input setup time, RMII_RXER valid before
RMII_REF_CLK High
-
Input hold time, RMII_RXER valid after
RMII_REF_CLK High
-
Output delay time, RMII_REF_CLK High to
RMII_TXD valid
16
16
5
td(REFCLK-TXEN)
Output delay time, RMII_REF_CLK High to
RMII_TX_EN valid
162
Peripheral Information and Electrical Specifications
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