RM46L450
RM46L850
www.ti.com
SPNS184 –SEPTEMBER 2012
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 5-20. SPI Slave Mode External Timing (CLOCK PHASE = 1)
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
8
SPIENAn
SPICSn
9
10
SPISOMI
Slave Out Data Is Valid
Figure 5-21. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)
Copyright © 2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
159
Submit Documentation Feedback
Product Folder Links: RM46L450 RM46L850