RM46L450
RM46L850
www.ti.com
SPNS184 –SEPTEMBER 2012
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI Data Is Valid
SPISOMI
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 5-18. SPI Slave Mode External Timing (CLOCK PHASE = 0)
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
8
SPIENAn
SPICSn
9
Figure 5-19. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)
Copyright © 2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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