ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ
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SLES080B – MAY 2003 – REVISED NOVEMBER 2003
I
L– (Pin 26)
L+ (Pin 25)
I
I
–
+
OUT
OUT
OUT+
Figure 25
Circuit
I
OUT
OUT
3
2
1
I
R– (Pin 18)
R+ (Pin 17)
I
I
–
+
OUT
OUT
OUT–
Figure 25
Circuit
Balanced Out
I
OUT
OUT
Figure 26. Measurement Circuit for Monaural Mode
APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE
V
DD
MONO
CHSL
DEM
V
2L
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
External
Filter
Device
AGND3L
I
I
L–
L+
3
OUT
WDCK
LRCK
DATA
BCK
4
OUT
DATA
BCK
SCK
AGND2
5
V
1
CC
6
Analog
Output Stage
(See Figure 23)
SCK
V L
COM
7
PCM1794
DGND
V
COM
R
8
V
DD
I
REF
9
MUTE
FMT0
FMT1
ZERO
RST
AGND1
10
11
12
13
14
I
R–
R+
OUT
I
OUT
AGND3R
V
CC
2R
Figure 27. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application
22