6.3 Socket Present State Register
This register reports information about the socket interface. Writes to the socket force event register (offset 0Ch, see
Section 6.4), as well as general socket interface status, are reflected here. Information about PC Card V
support
CC
and card type is only updated at each insertion. Also note that the PCI6x21/PCI6x11 controller uses the CCD1 and
CCD2 signals during card identification, and changes on these signals during this operation are not reflected in this
register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Socket present state
R
0
R
0
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Socket present state
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
X
R
0
R
0
R
0
R
X
R
X
R
X
Register:
Offset:
Type:
Socket present state
CardBus Socket Address + 08h
Read-only
Default:
3000 00XXh
Table 6−4. Socket Present State Register Description
BIT
SIGNAL
TYPE
FUNCTION
YV socket. This bit indicates whether or not the socket can supply V
PCI6x21/PCI6x11 controller does not support Y.Y-V V ; therefore, this bit is always reset unless
CC
overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.
= Y.Y V to PC Cards. The
CC
31
YVSOCKET
R
R
R
XV socket. This bit indicates whether or not the socket can supply V
PCI6x21/PCI6x11 controller does not support X.X-V V ; therefore, this bit is always reset unless
CC
overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.
= X.X V to PC Cards. The
CC
30
29
XVSOCKET
3VSOCKET
3-V socket. This bit indicates whether or not the socket can supply V
PCI6x21/PCI6x11 controller does support 3.3-V V ; therefore, this bit is always set unless overridden
CC
by the socket force event register (offset 0Ch, see Section 6.4).
= 3.3 Vdc to PC Cards. The
CC
5-V socket. This bit indicates whether or not the socket can supply V
PCI6x21/PCI6x11 controller does support 5-V V ; therefore, this bit is always set unless overridden
CC
by bit 6 of the device control register (PCI offset 92h, see Section 4.39).
= 5 Vdc to PC Cards. The
CC
28
5VSOCKET
RSVD
R
R
R
27−14
13 †
These bits return 0s when read.
YV card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
= Y.Y Vdc.
YVCARD
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
XV card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
= X.X Vdc.
12 †
11 †
10 †
XVCARD
3VCARD
5VCARD
R
R
R
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
3-V card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
= 3.3 Vdc.
5-V card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
= 5 Vdc.
†
One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
6−4
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